danieltyukov/aispice

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Quick start ·
Setup ·
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Changelog
What it does
aispice works on the LTspice schematics (.asc) in a folder. You describe a change in plain language; the agent reads the circuit, edits it, runs a simulation and checks the result against your specs before it answers. It comes in three forms that share one engine:
- a **desktop app** with the schematic, waveforms with cursors, a spec table, edit history and the chat side by side
- a **command line tool**, aispice, for chat, simulation, netlisting, linting and spec checks in CI
- an **MCP server**, aispice mcp, that gives Claude Code, Cursor, Codex, Claude Desktop or any other MCP client the same tools
What the agent can do with your circuits:
- read a schematic as parts, the net on every pin and the directives, so it reasons about circuits and not coordinates
- edit with typed operations (add, remove, move, rotate, set values, connect pins, label nets, change directives); aispice places parts and routes wires so the result stays readable in LTspice
- turn a SPICE netlist, or a circuit it reads from a picture, into a readable LTspice schematic, checked to netlist back to the same circuit
- simulate on **ngspice, LTspice, Xyce or Cadence Spectre**, and measure gain, bandwidth, phase margin, overshoot, settling time, rise time, RMS, noise density and integrated noise, PSRR, CMRR and more
- check a spec table and report pass or fail with margins, at one operating point or across process, voltage and temperature corners, naming the worst corner of each spec
- sweep parameters, run Monte Carlo analysis over part tolerances and device mismatch with yield, and optimise part values to meet several specs at once, at every corner if asked
- check the bias point of every transistor (region, gm, gds, gm/Id), find poles and zeros, start from 17 verified reference circuits, lint for wiring mistakes, and render the schematic to SVG or PNG
- design transistor-level IC blocks on a process design kit you have installed (IHP SG13G2 first): draw with the PDK's MOSFETs, resistors, MIM capacitor and HBT, simulate on ngspice or Xyce with the PDK's own models, size transistors by gm/Id from tables aispice builds and caches, and start from templates (current mirror, OTA, two-stage op-amp, comparator, bandgap, LDO) that meet their specs at every process corner
- lay those blocks out with generators that draw the PDK's own pcells (current mirror, differential pair, five-transistor OTA, two-stage Miller op-amp with its MIM capacitor, StrongARM comparator, drawn mirror-symmetric) with common-centroid or interdigitated units, dummies and guard rings; check them with the PDK's KLayout DRC and LVS decks; extract parasitics with Magic; and report every spec before and after layout
- describe blocks by behaviour and simulate them with the transistors and logic around them: Verilog-A models compiled with OpenVAF, Verilog co-simulated through ngspice's XSPICE (a comparator driving a counter, for one), and XSPICE gates and bridges between analog and digital nodes
- split a chip-level target into block specs with the equations shown (an ADC front end from ENOB to the OTA's gain, bandwidth and noise; an LDO from regulation and PSRR to its error amplifier), and prove a trimmed block can be trimmed into range at every corner and mismatch sample
- import xschem schematics (IHP's test benches among them) as readable .asc files and export .asc files to xschem with IHP's symbols, each conversion proven by netlisting both sides
- undo any edit; every change is saved as a snapshot
Things you can ask:
- Move the corner of this filter to 1 kHz using E24 values.
- Why does the output clip? Check the bias point.
- Size R1 and R2 for 20 dB of gain and at least 100 kHz of bandwidth.
- Run a Monte Carlo with 1% resistors and 10% capacitors and tell me the yield.
- Check the specs at the ss, tt and ff corners from -40 C to 125 C and tell me the worst corner.
- Add a 100k load at the output and show me what it does to the response.
Quick start
Install the command line tool (Rust 1.88 or newer) and a simulator:
Add a key for your model provider and check the setup:
Then ask about a folder of circuits: