skillhubVivado FPGA 全流程自动化
Drive Xilinx Vivado FPGA flow end-to-end from an AI agent: create/open a project, add RTL and constraints, run synthesis, place & route, generate bitstream, and parse timing (WNS/TNS) and utilization reports. Use whenever the user asks to build, synthesize, implement, or generate a bitstream for a VDevelopment
